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Mach1 Hardware Update (PCB 2.0)

Pantheon

Active Member
Developer
#1
mach1_assembled.png

In development, PCB 2.0 for the Mach1 platform.

Changes: migrated from SAM3U MCU TQFP-100 to BGA-144 version. Migrated logic controller MAX V to Lattice FPGA (BGA-256).

Design changes: SMC bus changed from 8-bit to 16-bit (buffer change from 32 bytes to 9216 bytes).

Availability: late December.
 

Pantheon

Active Member
Developer
#8
Further speed improvements in logic:

Initializing EXT I/O hardware board
EXT I/O board successfully initialized
Attempting to automatically detect Flash device
Mode NAND X8 returned ident code: 0xC2F1809502
Successfully detected device in SLC NAND mode
Connected to Flash (CHIP ID: 0xC2F1809502)
Flash detected: MXIC MX30LF1G18AC (134,217,728 bytes)
Programming mode: EXT I/O (Parallel)
Flash page size: 2048 bytes (64 bytes extended)
Device interface: NAND (X8 3.3V)
NAND block manager disabled
NAND memory map complete: 65,536 pages available for access
Beginning memory read from MXIC MX30LF1G18AC
Start address: 0 (0x00) Length: 134,217,728
Read operation complete
Read 134,217,728 bytes in 28.845 seconds, 4,653,067 Bytes/s
Opened file for writing: FlashcatUSB.exe, (size: 12,457,472 bytes)
Target Flash address: 0x00000000, bytes to write: 12,457,472 bytes
Beginning memory read from MXIC MX30LF1G18AC
Start address: 0 (0x00) Length: 134,217,728
Read operation complete
Read 134,217,728 bytes in 29.042 seconds, 4,621,504 Bytes/s
 
Last edited:

Pantheon

Active Member
Developer
#12
Production units are now shipping to users who did the EXCHANGE program.

I just did some testing with this MLC NAND Flash (MT29F64G08CBABA) and it has some very interesting results.

I wrote a file (25MB with very random data) and then did a verify:

fc_verify.png

Doing another verify produced this:

1550398947675.png

And you might think there is a problem. But you would be wrong! Its actually working as designed.

When you start getting into MLC (2-bit per cell) or higher, you will start to realize why MLC has major flaws: its unreliable. This is where ECC (error correcting code comes in). If you take a look at the datasheet:

ecc.png

40-bit ECC per 1KB~ of data! To put that in perspective, a typical SLC NAND has 1-bit to 4-bit per 512 byte. What this means, is per 8KB block, you will also need to write over 512 bytes of just ECC data to correct that 8KB on read back!

In the coming weeks I will be researching and working on ECC schemes used on more high end density MLC NAND devices.
 

Pantheon

Active Member
Developer
#13
Screenshot 2019-02-17 14.01.21.png

Screenshot 2019-02-17 13.59.57.png

I enabled ECC with Reed-Solomon and 4-bit correction. And now look at the result. It only has 3621 bytes incorrect (instead of the original 11,5xx).
 
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